This invention relates generally to wireless communication systems, and more particularly, to frequency synthesizers for wireless communication systems.
In current wireless communication systems, frequency synthesizers are the core components in the wireless devices. The phase noise performance together with the spurious content of these frequency synthesizers is of considerable importance because these factors have first order effects on the entire transceiver system of the wireless device. Accordingly, creating frequency synthesizers with very low phase noise and spurious content is very important in order to reduce these first order effects.
Fractional-N synthesizers with sigma delta shaping are commonly used in the wireless devices because sigma delta shaping provides the best performance available with integrated frequency synthesizers. In these synthesizers, a phase locked loop (PLL) frequency multiplication is used in which a feedback frequency divider modulus is dynamically adjusted to create an average multiplication factor that can be controlled with precision (much greater than that of the divider modulus). Further, configuring the device as a fractional-N device as compared to an integer N device allows the use of relatively large reference frequencies and PLL bandwidths because instead of providing only multiple integer steps in frequencies, as is the case in traditional synthesizers (e.g., integer-N synthesizer), smaller fractional steps in frequencies may be provided. The smaller steps allow a reference frequency step size to be significantly larger than an output frequency step size such that the loop bandwidth can be increased. Thus, using these fractional-N synthesizers, not only is oscillator noise effectively attenuated, but frequency switching is fast. However, this results in variation of the divider modulus that introduces instantaneous phase noise in the feedback loop, which loop modulates the voltage controlled oscillator (VCO) and accordingly contributes to phase noise. Frequency errors are seen as phase quantization noise that results from the coarse resolution of the divider. Additionally, noise shaping may be provided with a higher order sigma delta modulator that can be used in the control of the divider, which shifts most of the noise quantization energy bandwidth out of the PLL bandwidth. However, this shifting and channel spacing in fractional-N synthesizer introduces fractional spurs that adversely affect the performance of the transceivers.
More particularly, in fractional-N synthesizers spurs appear at phase frequency detector (PFD) offsets from the carrier. Additionally, the spurs also appear at frequencies equal to the channel spacing resolution and may also introduce sub-fractional spurs due to the way the sigma delta is implemented. Harmonics of all of these spurs may also appear. Performance of the system is thereby adversely affected. Thus, a need exists for mitigation of fractional spurs that arise due to the channel spacing or stepping in fractional-N synthesizers.